FIG. 1 illustratively shows the structure of one prior art node in a data communication network which has a plurality of nodes or stations such as terminals or workstations with data communication functions. The network is a Round-Robin type and is operated in a token-passing mode for serial data transmission between the nodes or stations over a bus type communication path.
Each node includes a processor 10 having a communication function, a bus control unit 30, and a malfunction detect/control unit 20. The bus control unit 30 interfaces the processor 10 with the bus and outputs a bus acknowledge signal to the processor 10 responsive to a bus request signal from the processor 10 when a token is passed to the processor 10 for the permission of access to the network. Also, the malfunction detect/control unit 20 detects a malfunction occurred in the network. If a malfunction is detected, the malfunction detect/control unit 20 provides a malfunction signal to processor 10 to stop the data transmission, and at the same time sends a blocking signal to the bus control unit 30 for disconnecting with the bus.
Referring now FIG. 2, the bus control unit 30 in the node comprises a Direct Memory Access Controller(DMAC) 31, a serial Data Input/Output Device(SIO) 32, a bus driver 34 and a bus control module 33. The DMAC 31 accesses parallel data stored in the memory of the processor 10 at a high speed over a system bus in the node, which permits fast data transmissions. The SIO 32 converts parallel data from the DMAC 31 into serial data for serial data transmission over the bus. The bus driver 34(for example, IEEE 488) provides a physical connection between the processor 10 and the network. The bus control module 33 in the node provides a bus acknowledge signal to the processor 10, when a token is given to the processor 10 after receiving a bus request signal from the processor 10. The bus control module 33 transmits data from the SIO 32 via the bus driver 34 to the bus, and data sent from other node in the network over the bus to the SIO 32. The system bus is a path for connecting elements such a memory, a processor, a DMAC and a SIO in each node.
The operation of the node for data transmission over the bus is explained below. The processor 10 starts to serially transmit data after receiving the bus acknowledge signal from the bus control unit 30 which allows the bus occupation for data transmission. The malfunction detect and control unit 20 includes a counter circuit, and is synchronized to be active with the bus acknowledge signal. The malfunction detect and control unit 20 serves to control the bus control unit 30.
For example, if the bus occupation by the processor 10 in a node exceeds the maximum bus asserting time for transmitting the preestablished number of data frames, then the malfunction detect/control unit 20 considers this as some malfunction of the node itself. Thus, the malfunction detect and control unit 20 outputs a malfunction signal to the processor 10 to stop the data transmission and a blocking signal to a bus control unit 30 to disconnect with the bus. As a result, the node releases the bus so that the next node may occupy the bus for data transmission.
Further in detail, the logic used by the processor 10 in data communication is described referring to FIG. 3. When the processor 10 has data to transmit, the processor 10 outputs a bus request signal to the bus control module 33. The bus request action of the processor 10 in the step of S101 is as follows.
The counting of the bus control unit 33 with assertion-synchronizing clock is continued to reach the preestablished value(for example, FFH) until a token is passed, then the bus is not occupied. At this time, the processor 10 which has requested the occupation of bus decides at the step of S102 whether a bus acknowledge signal is received. When the response is "yes", the DMAC and SIO is enabled at the step of S103. Then, the bus control module 33 outputs a bus acknowledge signal to the processor 10 and a bus asserting signal to the network over the bus and enable the bus driver 34 to connect with the bus. At this time, the processor 10 starts to transmit data over the bus(step S104) via the bus control unit 30. At the steps of S105 and S106, when the data transmission is completed, the bus control module 33 release the bus for the data transmission of another node in the next oder. If the data transmission is not yet completed in the step of S105, the steps of S104 and S105 are repeated until the data transmission is completed.
In the prior art, the detecting of malfunction in a network including a plurality of nodes is performed in the node which occupies the bus by checking the maximum occupation time of the bus allowed to the node to ensure an equal opportunity for the bus occupation to each node.
Hence, the prior art network cannot detect a malfunction caused by failure the network itself. Also, the prior art network cannot monitor the malfunction in each node and cannot be recovered from the malfunction when the network itself is malfunctioned.
Referring now to FIG. 2 and FIG. 3, the prior art network for data transmission functions such that after sending a bus-request signal to initiate the data transmission over the bus the processor waits until a bus acknowledge signal is received, and therefore time delay occurs for the data transmission process because a bus-request signal is produced during operation of the program, while the bus-acknowledge signal is produced randomly so that the controlling of the bus would also be random. Thus, no regularity of the bus request signal with the bus acknowledge signal prevents stable control for data transmission. The additional control for confirming a bus-acknowledge signal is needed, which causes delay of the data transmission.